What is GPU RAM?
GPU RAM is the large memory pool, anywhere from a few gigabytes to a few hundred, that every Streaming Multiprocessor on the die can address. It's also called video RAM (VRAM), and it's built from Dynamic RAM (DRAM) cells: denser and cheaper per bit than the Static RAM (SRAM) used in on-chip registers and cache, but slower to reach.
On most GPUs, RAM sits on a separate chip from the compute die entirely. Recent data center GPUs like the H100 instead place it on a shared interposer next to the die, shortening the path and raising bandwidth, using High-Bandwidth Memory (HBM) rather than the DDR memory found in consumer cards and CPUs.
This is the pool CUDA's programming model calls global memory, and it's also where data spills to once a kernel's working set outgrows the on-chip register file. An H100, for example, ships with 80 GiB of it. Run nvidia-smi on a live box to see how much is actually free before launching a job, or compare capacity across listings on Aquanode's marketplace before sizing a deployment.
Building on GPUs? Aquanode runs the workload.
Deploy on H100, H200, B200, A100 and MI300X across a multi-provider marketplace, without racking your own hardware or committing to one cloud's spec sheet.
See also
Memory Coalescing
Memory coalescing is a hardware technique that folds several threads' logical memory reads into one physical DRAM access. Why it exists, how it maps onto a warp, and a benchmark showing what a bad access pattern costs.
Streaming Multiprocessor
A Streaming Multiprocessor is the closest thing an NVIDIA GPU has to a CPU core, but far simpler and far more numerous. How SMs trade per-thread sophistication for massive parallelism and near-free context switching.
nvidia-smi
nvidia-smi is the command line tool for querying and managing NVIDIA GPUs, built on the NVML management library. What it reports, what it can change, and why its text output isn't a stable interface.
GPU Architecture
How NVIDIA GPUs are actually built, from Graphics Processing Clusters and Streaming Multiprocessors down to the memory hierarchy, and how Ampere, Hopper, and Blackwell differ.
